Low-power today is at the forefront of SoC design challenges. Whether to cut energy consumption, reduce heat dissipation, or extend battery lifetime, the focus has shifted from traditional constraints such as area and performance to include new constraints around power consumption.
Most power reduction techniques operate at the physical level, during or after RTL synthesis. Yet most power consumption is determined at the architecture level and during RTL creation. It is therefore essential to consider power during the earliest stages of the design cycle.
This 2-hour workshop presents a fully automated and silicon-proven flow to explore, estimate and optimize switching and leakage power from the architecture level to the RTL. When most power flows focus on measuring power, Calypto Design Systems has engineered an innovative solution pin-pointing power inefficiencies, advising surgical RTL design optimizations and implementing them automatically. By attending this event you will learn how to achieve decisive power savings for your next SoC.
Click on the link to register.