|FPGA Design Series: Synthesis Issues
Does it seem like sometimes the tools that are meant to make you more efficient actually slow you down? Perhaps you're like many of the FPGA designers who report that synthesis-induced bugs dramatically increase bring-up time for FPGAs. Are you struggling to use current tools to debug and bring-up increasingly complex FPGAs? The bottom line is, synthesis often makes FPGA design harder than you thought.
|Synthesis is one of those steps in FPGA design that's deceptively complex and time consuming for a number of reasons:
- Synthesis sometimes mistranslates RTL, introducing bugs
- Synthesis is required to program the FPGA each time you iterate on a design
- Synthesis pragmas may cause the FPGA-based design to differ from RTL simulation
Imagine your FPGA is a wall of bricks (an accurate description for an FPGA that won't come up in the lab). Each brick is a block in your design. When a brick-layer builds a wall, he uses a level to verify that each brick sits properly and tha
t the whole wall is true and plumb. Well, if a level isnt... level... the wall will never be right. In FPGA design, synthesis is supposed to make and connect each block so it is true to the design intent. But that's not always the case.
If your synthesis tool is part of your level, each time you use it to make a change in your FPGA, you may be chasing errors induced by synthesis pragmas and optimizations and not improving your design. Going back to fix a brick and re-using the same unreliable level to replace it properly is obviously not a fast way to get a true and plumb wall - it's also not a fast way to debug your design considering a synthesis, place and route run can take 8 to 18 hours!
While design blocks are more complex than bricks, using less than the most reliable model of your design creates uncertainty that adds days and weeks to debugging your design. Eliminating the uncertainty and time introduced by repeat synthesis runs is a much smarter, faster way to bring up today's advanced FPGAs. How? Use your simulator, not your synthesis tool for the 'level' in your FPGA verification process. GateRocket Device Native® technology enables rapid FPGA verification and eliminates much of the time by exposing inaccuracies introduced by synthesis.
|A Better Level: Fast, Flexible and Accurate|
In FPGA design, the perfect measure of accuracy is the FPGA itself. And the most flexible way to place and adjust design blocks is the simulator. Using the FPGA and the simulator together provides device-level accuracy and the most rapid technique for bringing up and debugging today's FPGA designs. That's GateRocket's approach. Synthesize and route the FPGA once and then use the FPGA together with the software simulator to correct any problems, only re-synthesizing when the design is performing correctly. Debug and bring-up without repetitive synthesis and routing cycles. It's the fastest way to make your FPGA work the way you want it to.
|The GateRocket® RocketDrive® has been developed to solve FPGA design process problems like long, repetitive synthesis runs and synthesis-induced bugs. RocketDrive bridges the gap between RTL and FPGA by putting your FPGA into your simulator and giving you the tools you need to move back and forth between RTL and FPGA without guessing, re-synthesizing and re-routing. Finding issues caused by synthesis optimizations becomes simple with RocketDrive and doesn't require long loops through synthesis and routing each time you want to examine and debug different parts of the design.|