Ultra HDI e-bulletin -- September 2023

ASC now has the capability to fabricate ultra HDI technology, providing feature sizes well below what is achievable with traditional subtractive etch processing. We are reaching out to industry experts to ask for their opinions and advice on how to best take advantage of these new capabilities.

Ultra HDI Design Capabilities
August 2023 Ultra HDI e-bulletin
Featured Interview

Gene H. Weiner is a business and technical consultant, heading Weiner International Associates.

He serves the specialty chemical and electronics industries, including Fortune 100 companies. Mr. Weiner’s executive experience includes: president of a leading supplier of copper-clad laminates, vice president of one of the world's leading suppliers of photopolymers and specialty chemicals, and vice president of a major specialty chemical firm. Gene Weiner pioneered additive circuitry with fine lines producing a print wired memory plane in the 1950s. Click Here for Gene’s Full Bio

Industry awareness of ultra HDI is growing, and a significant share of the market is looking into designing with these ultra-fine features. Why do you feel that this new technology is important to the industry?


Ultra HDI circuitry advances the sought-after smaller, lighter, faster, and more reliable electronic devices provided by HDI interconnects. It is critical for advancing performance in a wide range of computing, medical and military devices. It is essential for the development of organic substrates for packaging chiplets.


Ultra HDI parts would enhance the performance of HDI boards currently in demand to make the circuitry needed by the rapidly growing AI market and its need for faster data processing.


Growth for Ultra HDI circuits in Asia, where manufacturing processes and facilities currently exist, is forecasted by some to be 10-12% per year for the next few years - more than double that of “ordinary” PCBs.



What key information points are critical to shortening the cycle for adoption - to more quickly begin taking advantage of the benefits of ultra HDI?


Let’s start by removing the word quickly from the question.

The desired performance and features must first be defined. Set goals and milestones. Determine at the outset whether the designed part will be for a small niche market or volume production. Be sure that funding and patience are adequate for the project. Leave any NIH complex behind.


Then form a team (“partnership” created) comprising the end user, board assembler, fabricator, and designer. The designer must understand what the fabricator can and cannot do. The assembly company must also understand the process and how part layout, board design, and manufacturability relate.


Very few fabricators in the U.S. are equipped to make HDI or Ultra HDI circuits. They must understand the materials available for the process and their limitations. All, to a practical extent, must be familiar with and use advanced design tools such as IPC-2581 or ODB++ and create a digital twin to efficiently generate a manufacturable part.


Overcommunicate. All must participate in the process from design to final test.


Regarding the term “quickly”: several end users with similar feature size needs should participate at the same time, in order to establish an acceptable performance/test standard for each. Their results, and/or the benefits achieved should be presented in as many trade journals, papers and conferences as possible. Each featuring something slightly different and each laying out the benefits achieved.


Remember, nothing breeds success like success!


As an expert that has navigated through multiple waves of technology advancements, what advice to you have for those who are looking at learning new techniques?


As a manager I have had to make many decisions on funding activities, acquisitions, R&D programs, licenses and manpower commitments. I recommend attending as many related conferences as possible; also webinars, and courses relating to the topic of interest.

 

Keep an open mind. Ask questions. There are no dumb questions – just dumb answers! Read available reports and articles. Discuss with your peers and work associates. Understand what benefits would be provided for like and/or not-in-kind technology or existing products.

Find out what similar activities failed and why.

 

Check the data. Recheck the data. Then evaluate risk versus reward.

 

Once again: be sure that your program is adequately funded!


What are your outside interests - the hobbies that help you reboot?


I enjoy digging in the dirt (gardening herbs and vegetables) and love a day at sea fishing. I like

to participate in community activities and have served on several local Boards: The Plymouth Philharmonic Orchestra, The Speakers Group at the Pinehills, etc.

ASC Capabilities
Technology Highlight

Join me at PCB West at the following free session:


Wednesday, Sept 20 from 3:30-4:30pm


F7. Ultra-High Density Interconnects - A New Horizon for North American Manufacturing

Speaker: John Johnson, American Standard Circuits


The presentation will discuss ultra-high density interconnects from a board fabricator's perspective. Covered will be the technology approach and manufacturing processes used to manufacture ultra-high-density interconnects with 25 micron and smaller line width/spacing. Design approaches to minimize complexity, increase reliability and areas of concern in use of various design solutions will be presented.


https://pcbwest.com/conference-program-2023/

Ask how we can enable new Design freedoms for your work on Defense, Medical, and Commercial applications:


Contact John Johnson at jjohnson@asc-i.com

Frequently Asked Questions

Q: What is the minimum spacing from trace to pad (external layer)?


A: That depends on how pads are defined by soldermask - If pads are mask defined, spacing can be as low as 25 micron. If defined by the copper, then other features need to be at least 50 microns away, preferably 75 microns.


The copper to copper spacing can add costs in subtractive etch processes. In the semi-additive environment, this is not the case.



  1. On inner layers, spacing could be 25 microns or below.
  2. For outer layers, there must be enough space to allow the soldermask to fully cover the trace and not expose any copper. If the mask defines the pad, the coverage is not an issue so 25 micro can work. If not, mask registration allowances need at least 50 micron spacing or more.


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