In 1966 Abraham Maslow famously said, “I suppose it is tempting, if the only tool you have is a hammer, to treat everything as if it were a nail.” Well, the current supply chain challenge has placed many of our hammers out of reach. Our favorite micro controllers, DSPs, transistors, etc. are now facing 50-week delays, minimally, and design engineers are forced to either wait out this painful drought, or find alternative means of keeping their products afloat.

Although there truly are designs that are highly dependent upon the availability of key components, there remain many designs, or portions of designs, that would still be viable even if built with alternative design topologies. The first step in this process is to cognitively separate the design objectives from the design methods, and to clearly define these. We all have our favorite tools, but far too often our favorites become our primary, or even our only, choice for solving problems – every signal analysis problem requires a DSP; every high-speed application requires an FPGA or SoC; every power design requires our favorite DC-to-DC brick. By separating the objectives from the methods, we can begin to see that there are other ways, perhaps these ways are unfamiliar to us, but they are valid approaches, and they could allow our designs to become more resilient towards supply chain woes.

Most signal analysis applications have two primary parts: 1) isolate a band of frequencies within a data stream; and 2) perform mathematics processes upon these bands to make decisions. If a high-performance DSP, or ADC is not available, then such a design may be forced to use more generic components that lack the performance specifications we are used to. In these cases, a well-designed analog front end (AFE) can offload a portion or all of the duties the DSP used to handle.

Band isolation can be achieved using a band-pass filter and an active peak detector. In fact, if several bands are needed, there can be an array of filter-to-detector designs. When the outputs of the peak detectors reach a critical amplitude, the raw signal can then be further processed.

To further expand upon this approach, recall that operational amplifiers offer a huge variety of signal conditioning choices: integration, differentiation, adding, subtracting, phase shifting, etc. Through a careful selection of circuitry, a majority of the computationally-intensive processing can be addressed with analog circuitry so that so that you can reduce computation time and your generic MCU can efficiently make decisions

Many complex devices require a power management IC (PMIC) to ensure the proper sequence, timing and slew rate control of multiple voltage rails. PMICs are wonderful, and ease the power system design process… as long as they are available.

A majority of power management applications require the connecting and disconnecting of power rails at precise times. Discrete P-channel FETs and PNP transistors can be utilized to achieve similar performance to an integrated, yet unavailable PMIC.

Such a topology (Figure above) can be used over a wide array of applications. In this figure, sequencing is achieved through the XMEGA MCU, however, this could also be the Power Good signal of another regulator, or another trigger that is useful in timing enforcement.

By adding some additional passive components, the simple high-side switch can be changed to offer slew rate control. This can be very useful, especially when switching on nodes with substantial capacitance.

Temperature sensing ICs offer high accuracy and precision. However, if these sensors are not available, there are low-cost options, which can offer reliable performance. The circuit above illustrates a simple temperature sensor that could work for most applications. The operation is simple:

1.      Initially, the source voltage for the thermistor is at 0V. This is achieved by driving and holding PIN 11 (GPIO 17) LOW for at least five time constants.

2.      The driving pin (PIN 11 (GPIO 17)) is toggled HIGH, and an internal timer is started.

3.      The comparator should be set for a value that reflects the passage of a specific number of time constants. For example, if this were a 3.3-V system, then the passing of 1 time constant would produce a voltage of 3.3 V * 0.632 = 2.086 V.

4.      Once this voltage is exceeded on PIN 15 (GPIO 22), the timer is stopped and the counts are used to determine the amount of time this circuit took to reach this voltage.

5.      Using this and the thermistor’s datasheet, the temperature can be determined.

6.      This process can be repeated over and over again to produce fairly accurate and precise temperature measurements.

Undoubtedly, the supply chain challenges have been a burden for engineers, and there are no easy answers for addressing these. However, in the pursuit of pin-compatible, performance-compatible alternative components, be sure that low-tech options are not brushed aside. Such design options can be implemented quickly, can be lower risk than qualifying a new complex integrated component, and can help to get your product unstuck from these supply chain woes.

 DocJC, "AvrFreaks," Atmel, 19 Jan 2019. [Online]. Available: https://www.avrfreaks.net/forum/hi-side-fet-switch-low-voltage. [Accessed 21 March 2022].

Mosaic Industries, "Mosaic Documentation Web," Mosaic Industries, 15 03 2013. [Online]. Available: http://www.mosaic-industries.com/embedded-systems/microcontroller-projects/electronic-circuits/push-button-switch-turn-on/inrush-current-limited-mosfet. [Accessed 21 03 2022].

David, "Simple Thermometer Using RC Circuit," Thorn IT Solutions, 10 July 2021. [Online]. Available: https://thornitsolutions.wordpress.com/2012/07/10/simple-thermometer-using-rc-circuit/. [Accessed 21 March 2022].

-NM

In the past decade, the revival of deep neural networks has led to dramatic success in numerous applications ranging from computer vision, to natural language processing, to scientific discovery and beyond. Nevertheless, the practice of deep networks has been shrouded with mystery as our theoretical understanding for the success of deep learning remains elusive. In this talk, we will focus on the representations learned by deep neural networks. For example, Neural collapse is an intriguing empirical phenomenon that persists across different neural network architectures and a variety of standard datasets. This phenomenon implies that (i) the class means and the last-layer classifiers all collapse to the vertices of a Simplex Equiangular Tight Frame (ETF) up to scaling, and (ii) cross-example within-class variability of last-layer activations collapses to zero. We will provide a geometric analysis for understanding why this happens on a simplified unconstrained feature model. We will also exploit these findings to improve training efficiency: we can set the feature dimension equal to the number of classes and fix the last-layer classifier to be a Simplex ETF for network training, reducing memory cost by over 20% on ResNet18 without sacrificing the generalization performance.