Custom Silicon Solutions and SoC IP Bulletin | Q3 2021 Update
Greetings!
 
As we enter the final quarter of 2021, the delta surge has reduced, and a return to a new normal, while not guaranteed, appears to be within sight. We look forward to reconnecting with you at our upcoming Q4 events. 
 
New custom SoC design starts continue to be propelled by AI-enabled hardware for cloud and edge applications. At OpenFive, we’re seeing a fast growing trend among our customers for chiplet based SoCs with die-to-die (D2D) interfaces in 5nm and 6/7nm, and multi-die packaging using CoWoS and inFO_Os technologies. These new connectivity solutions are fueled by the insatiable demand for higher bandwidth and lower latency systems. 
 
Our teams at OpenFive are innovating and investing in leading-edge IP and subsystems such as 5nm, 2.5D advanced packaging, die-to-die interfaces, chiplets, HBM3/2E, LPDDR5, CXL subsystems, and AI Vision SoC platforms. You can learn about these in our quarterly newsletter, the OpenFive Bulletin.

 
Sudhir Mallya
VP Product Marketing & Business Development, OpenFive 
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OpenFive AI Vision Platform
 
OpenFive’s Edge AI Vision platform enables you to build your own Edge AI SoC. Pre-configured subsystems allow you to focus on your key differentiators. Add your own custom accelerators, customize the subsystems, and mix and match different interfaces to meet your application’s unique requirements...Learn more...
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OpenFive Die-to-Die (D2D) IP Subsystem

OpenFive’s Die-to-Die Controller IP offers a unique value proposition in terms of low power, high throughput, and low latency links enabling faster time to integration for heterogenous chiplet connections in wired communications, AI, and HPC applications...Learn more...
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On-demand Webinars
On-demand Resource
RISC-V Chiplets, Disaggregated Die, and Tiles (Blog)

Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer both advanced workload performance and efficiency benefits.
The technology industry is shifting to custom designs, replacing traditional general-purpose CPU and discrete accelerator platforms. Instead, the computing platform can implement application-specific processing requirements at many levels, down to the instruction set architecture (ISA).
OpenFive LPDDR5/4X PHY (Product Brief)
 
LPDDR5/4X is the next generation low-power memory which boosts 2X faster data transfers than its predecessor. LPDDR devices can transfer data at higher rates with remarkable power efficiency. It also supports a unique low power feature, deep sleep mode (DSM), to reduce standby power even further.
LPDDR memories are used where area and power savings are key requirements. LPDDR also offers higher bandwidth compared to DDR counterparts. LPDDR5/4X is ideally suited for next-generation computing for AI Inference, Edge, IoT, Automotive, and Mobile applications. Download the product brief.
InFO_oS Implementation using Allegro Package Designer (Technical Paper)
 
A brief introduction of an advanced wafer level technology named Integrated Fan out (InFO) is covered as it provides high speed, low cost, low power consumption, small form factor, and energy efficiency. This paper explains various steps involved in implementing the InFO design in Allegro Package Designer tool from Cadence like taking in the constraints and pad stacks, placement of dice, bumps placement, assignment, and routing. Download the technical paper.
High Speed Signal and Timing Qualification Flow using SPICE in PnR (Technical Paper)
 
The data hand-off of mixed-signal IPs (Digital – Analog & Analog – Digital) designs are steadily increasing in complexity due to high-speed requirements, half cycle requirements, zero cycle requirements, and data bus structures which have stringent zero skew requirements. The Analog and Digital blocks are integrated in the PnR (Innovus) environment for most of the IPs. Download the technical paper.
Past Industry and Partner Events
September 8, 2021
CadenceLIVE India
Virtual Event
OpenFive presented two technical papers on the following two topics:
1. InFO_oS Implementation using Allegro Package Designer.
2. High-Speed Signal and Timing Qualification Flow using SPICE in PnR.

September 15, 2021
GF Technology Summit
NA, USA - Virtual Event

September 15 - 16, 2021
Design and Reuse IP SoC
China - Virtual Event
OpenFive presented a paper on the topic "适用于数据中心及HPC应用中所有AI SoC 的D2D IP方案 (D2D IP solution for all AI SoCs in data centers and HPC applications)".
 
September 16, 2021
GF Technology Summit Europe
Virtual Event

October 12, 2021
CadenceLIVE China
Virtual Event
 
October 19, 2021
CadenceLIVE Europe
Virtual Event

October 26, 2021
TSMC OIP Ecosystem Forum NA, USA
Virtual Event

October 27, 2021
TSMC OIP Ecosystem Forum China
Virtual Event

Upcoming Industry and Partner Events
October 27, 2021
TSMC OIP Ecosystem Forum Europe
Virtual Event

November 11 - 12, 2021
CSIA-ICCAD 2021 Annual Conference & Wuxi IC Industry Innovation and Development Summit 
China - In-person Event
OpenFive will be exhibiting and also presenting a paper on the topic “新世代芯片互联技术,重新定义系统设计 (Next-Generation Chip Interconnection Technology Redefines System Design)”.
 
December 1 – 2, 2021
D&R IP SoC Day
Grenoble, France – In Person
December 9, 2021
GSA Awards 2021 NA, USA
Virtual Event

December 5 - 10, 2021
Design Automation Conference (DAC)
San Francisco, USA - In-person | Virtual Event
(Dec 5 – Dec 9 In-person and Virtual Dec 7 – 10)
Besides exhibiting its products and solutions, OpenFive will also be presenting a paper on “AMS Verification for HBMPHY, a real case example of HBMPHY taped out and Challenges associated with 12nm AMS Verification”.

December 13, 2021
SemIsrael Israel
In-person Event

Visit https://openfive.com/resources/ for more on-demand resources
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About OpenFive
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OpenFive — your proven path from custom SoC architecture to volume silicon. OpenFive offers end-to-end expertise in Architecture, IP Integration, Design Implementation, Software, Silicon Validation, and Manufacturing to deliver high-quality silicon in advanced nodes down to 5nm.

With spec-to-silicon design capabilities, customizable platforms, and differentiated IP for Artificial Intelligence, Datacenter/High-Performance Computing, Networking, and Storage applications, OpenFive is uniquely positioned to deliver highly competitive domain-specific SoCs customized for your application. Visit www.openfive.com to learn more...

For any questions and comments, you can email us at info@openfive.com
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