The proposed multiport network method is a new paradigm for reconfigurable intelligent surface (RIS) design that focuses on the structural design of the intelligent surface element. The proposed multiport network method offers a new paradigm for reconfigurable intelligent surface design, significantly improving design efficiency by replacing computationally expensive EM simulations. Each RIS element is discretized into an initial multiport structure with multiple patches connected by discrete ports which may be either passive or tunable. Optimization algorithms obtain the optimal load impedance parameters for the internal ports to find the most suitable structure for the element.

This article proposes a novel analytical framework, denoted the multiport analytical pixel electromagnetic simulator (MAPES). MAPES enables efficient and accurate prediction of the electromagnetic (EM) performance of arbitrary pixel-based microwave (MW) and radio frequency integrated circuit (RFIC) structures. Unlike the internal multiport method (IMPM), which optimizes only connecting elements within a fixed, gap-separated pixel skeleton, MAPES operates directly on the all-pixel presence/absence formulation used in recent MW/RFIC design. By introducing virtual pixels and diagonal virtual pixels and inserting virtual ports at critical positions, MAPES captures all horizontal, vertical, and diagonal EM couplings within a single multiport impedance matrix. Only a small set of full-wave is needed to construct this matrix. MAPES provides a practical and versatile tool for AI-assisted MW & RFIC design across diverse technologies.

This article presents an automated design framework for broadband power amplifiers (PAs) based on a graph-driven evolutionary optimization approach. In the proposed framework, the input and output matching networks are represented as graphs and jointly synthesized in both the topology and parameter spaces to optimize the small- and large-signal performance of the PA. This approach enables the automated synthesis of physically realizable broadband source and load impedance trajectories without relying on predefined circuit templates. In addition, a graph-to-layout generation methodology is introduced to automatically translate the evolved circuit graphs into manufacturable layouts while incorporating electromagnetic (EM)-aware optimization. The proposed framework is experimentally validated through the design and fabrication of a 10-W GaN PA operating from 3.2 to 4.3 GHz and supporting 1 GHz instantaneous modulation bandwidth across the 5G NR n77 band.

This letter proposes an automated synthesis framework for compact broadband power amplifiers (PAs), driven directly by large-signal electromagnetic (EM) circuit cosimulation. To break the rigid geometric restrictions of conventional rectangular topologies while avoiding the self-intersections typical of unconstrained designs, a partially constrained parametric polygonal framework is proposed under a strict footprint boundary. This technique intrinsically realizes adaptive layout meandering to ensure both miniaturization and fabrication reliability. For validation, a 0.7–3.1-GHz broadband PA is fabricated. Measurements demonstrate a 41.9-dBm maximum output power (Pout) and a 72.9% peak drain efficiency (DE). Notably, the PA occupies an ultracompact footprint of 36×58 mm2.