Part 2 in this series details the serial link routing process. How does the process change with data rate? …which stubs are problematic? Have a look, and be sure to forward to your layout team too.
Thought you needed the board layout of your DDRx DIMM? Not so. This AppNote shows you how to use the EBD supplied with your models as a PCB in both pre- and post-layout simulation.
As designs move faster than 10 Gbps it becomes important to manage not only trace impedance but also via impedance. This can be challenging, because the typical via impedance range varies 4x compared to trace impedance.
PAM4 is ready-to-simulate in this QCD Design Kit. Models, masks, and topologies included.  CEI-56G-LR and CEI-56G-VSR.
Some discontinuities are unavoidable, yet some can – and need to – be removed. How do typical discontinuities affect system-level performance? Read pages 19 and 20 to find out.
DDR nets are single-ended with multiple loads, stubs, more ringing than loss, EQ on only one end – not your typical serial link. Can we achieve a decent BER in a context like this? Explore Skew_Eye_Latch and next generation DDR signaling and analyses in this Kit.